The present application relates to semiconductor device fabrication, and more particularly to fabrication of gate spacers for fin field effect transistors (FinFETs) with tighter fin pitches.
FinFETs are a desired device architecture due to their fast switching times and high current densities. In its basic form, a FinFET includes a source region, a drain region and fin-shaped channels located between the source and the drain regions. A gate electrode formed over the fins regulates electron flow between the source and the drain regions. A gate spacer is typically formed on sidewalls of the gate electrode to control gate-to-source/drain spacing. Devices with a narrow spacer width exhibit better performance (drive current) because of a lower series resistance. However, devices with a larger spacer width are better for short channel effect (SCE) control. The spacer width thus needs to be optimized for performance and SCE control.
The spacer width optimization in FinFETs becomes increasingly challenging as the fin pitches are scaling down. As the fin pitch decreases, a gate spacer layer from which the gate spacer is formed can merge neighboring fins, which makes the complete removal of the spacer material from the spaces between the fins difficult. Any remaining spacer material between fins can block the formation of the source and drain regions, killing yield. Therefore, there remains a need to develop a novel gate spacer structure that allows optimization of the spacer width to improve performance of FinFETs with tighter fin pitches.